1. Field of the Invention
The present invention relates in general to a memory core circuit for a static random access memory (SRAM), and more particularly to a bit line load circuit of the memory core circuit.
2. Description of the Prior Art
Referring to FIG. 1A, there is shown a circuit diagram of a conventional bit line load circuit of a memory core circuit for a SRAM. It should be noted herein that only one column of the memory core circuit, is shown in FIG. 1A.
In FIG. 1A, the bit line load circuit is designated by the reference numeral 11. The bit, line load circuit comprises a pair of P-channel MOSFETs Q1 and Q2 adapted to clamp a voltage difference between bit, lines B and /B at a predetermined level in a data reading operation. The bit lines B and /B have the opposite levels. Namely, the bit line B is active "high" and the bit line /B is active "low".
However, the conventional bit line load circuit has a disadvantage in that a direct current (DC) static current flows in a data writing operation because the P-channel MOSFETs Q1 and Q2 always remain at their ON states. Namely, in the data writing operation, data input transfer signals D and /D of the opposite levels are transferred respectively to the bit lines B and /B through a Y-pass gate, which is comprised of transistors Q3-Q6. The Y-pass gate acts to perform a column selection. In this case, one of the data input transfer signals D and /D has data of logical "1" and the other has data of logical "0". As a result, any one of the data input transfer signals D and /D necessarily has data of logical "0" and the DC static current flows along the "0" data path.
For example, in the case where data of logical "1" is to be written, the data input transfer signal D becomes logical "1", the data input transfer signal /D becomes logical "0" and a write enable signal WE becomes logical "1". Subsequently, transistors Q7 and Q8 are turned on, a signal Y of the selected column goes logical "1" and a signal /Y of the selected column goes logical "0". As a result, the transistors Q3-Q6 are turned on, thereby causing the DC static current to be continuously consumed through the path of the transistors Q2 and Q4 and Q6 and Q8.
On the contrary, in the case where data of logical "0" is to be written, the DC static current consumption path is formed along the transistors Q1 and Q3 and Q5 and Q7 in the opposite side to that in the logical "1" data. In result, the DC current is always present in the data writing operation. The current consumption is doubled in a product of a multi-bit manner.
Referring to FIG. 1B, there is shown a circuit diagram of another conventional bit line load circuit, which has been made in view of the above problem with the conventional bit line load circuit of FIG. 1A. In this drawing, the bit line load circuit is designated by the reference numeral 12. As shown in this drawing, the write enable signal WE is applied to gates of the transistors Q1 and Q2 so that the transistors Q1 and Q2 can be turned off in the data writing operation. The transistors Q3 and Q4 are small in size and always remain at their ON states to compensate for a leakage current in the data writing operation. However, in this case, the DC current flows through the transistors Q3 and Q4, resulting in a failure in the perfect blockage.